The present invention relates to amplifying solid-state imaging devices and to a technique for achieving a low-noise amplifying solid-state imaging device with small-sized pixels.
Conventionally, an amplifying solid-state imaging device, which has a pixel section provided with an amplification function and a scanning circuit provided at the periphery of the pixel section and reads image data by means of the scanning circuit, has been proposed as an amplifying solid-state imaging device. In particular, an APS (Active Pixel Sensor) type image sensor having a CMOS (Complementary Metal Oxide Semiconductor) structure advantageous in integrating the pixel construction with a peripheral driving circuit and a signal processing circuit is known.
The APS type image sensor is normally required to form a photoelectric conversion section, an amplification section, a pixel selection section and a reset section in one pixel. Therefore, three to four MOS transistors are employed besides the photoelectric conversion section normally constructed of a photodiode in the APS type image sensor.
However, if three to four MOS transistors are necessary per pixel, then the arrangement becomes a limitation on reducing the pixel size, and therefore, a method for reducing the transistor count per pixel is proposed (refer to, for example, JP 09-46596 A).
FIG. 14 shows a circuit diagram of the essential part of the amplifying solid-state imaging device in which the transistor count per pixel is reduced. The amplifying solid-state imaging device is constructed of a photodiode 101, a transfer transistor 102 for transferring a signal charge accumulated in the photodiode 101, a reset transistor 131, an amplification transistor 132 and a pixel select transistor 133. In this case, it is known that it is possible to have an extremely low noise and obtain a high-quality image if the photodiode 101 is of the buried type and the signal charge transfer from the photodiode 101 is complete.
FIG. 15 shows a timing chart of the operation of the amplifying solid-state imaging device shown in FIG. 14.
As shown in FIG. 15, during a period T1, a drive pulse φR(m) applied to the gate of the common reset transistor 131 goes high level to turn on the reset transistor 131, and the voltage level below the gate is raised. Consequently, the charge moves to the drain side of the common reset transistor 131 by a common signal charge storage section 108, and the voltage of the signal charge storage section 108 is reset to a power supply voltage VDD.
During the next period T2, the drive pulse φR(m) applied to the gate of the common reset transistor 131 goes low level to turn off the reset transistor 131. However, a drive pulse φS(m) applied to the gate of the common pixel select transistor 133 goes high level to read a reset level to a signal line 135 via the common amplification transistor 132 since the pixel select transistor 133 is in ON state. At this time, the amplification transistor 132 and a constant current load transistor 134 forms a source follower circuit.
During the next period T3, the drive pulse φS(m) applied to the gate of the common pixel select transistor 133 goes low level to turn off the pixel select transistor 133, and a drive pulse φT(m,1) applied to the gate of the transfer transistor 102 of a m-th row goes high level to enter the ON state to raise the potential at the gate. Consequently, the signal charge accumulated in the photodiode 101 of the (m,1)-th row is transferred to the signal charge storage section 108.
During the next period T4, the drive pulse φT(m,1) applied to the gate of the transfer transistor 102 of the (m,1)-th row goes low level to turn off the transfer transistor 102. However, the voltage during the signal charge transfer is held in the common signal charge storage section 108, and the signal level of the (m,1)-th row is read to the signal line 135 via the common amplification transistor 132 since the drive pulse φS(m) applied to the gate of the common pixel select transistor 133 goes high level and in ON state.
Then, after one horizontal scanning period (1H), the signal charge from the photodiode 101 of the (m+1)-th row is conducted to the common reset transistor 131, the amplification transistor 132 and the pixel select transistor 133 via the transfer transistor 102 of the (m,2)-th row for the pixel of the (m,2)-th row, and operation similar to that in the periods T1 through T4 is to be executed.
The above construction and operation are configured to have 2.5 transistors per pixel in the case of one common section per two pixels or have 1.75 transistors per pixel in the case of one common section per four pixels. That is, in these examples, the transistor count per pixel can be reduced.
However, the conventional amplifying solid-state imaging device causes the following problems in terms of the construction and operation. That is, assuming that the capacitance of the common signal charge storage section 108 is CFD, then a charge voltage conversion rate η for converting a signal charge ΔQsig from the photodiode 101 into a voltage signal ΔVsig is expressed by:η=G·ΔVsig/ΔQsig=G/CFD where G represents the gain of the source follower circuit constructed of the amplification transistor 132 and the constant current load transistor 134 and normally has a value (0.8 to 0.9) slightly smaller than one. It is necessary to reduce CFD in order to increase η. The capacitance CFD of the signal charge storage section 108 is the sum total of the junction capacitance on the drain side of the transfer transistor 102 connected to the signal charge storage section 108, the gate capacitance of the amplification transistor 132 and the junction capacitance to the substrate. Accordingly, there is a problem that the charge voltage conversion rate η is reduced as number of photodiodes and the transfer transistors connected to the common signal charge storage section increases.